This invention relates generally to a computer with a reduced instruction set, and more particularly to such computer having an improved instruction fech system and a segmented cache memory with predecoded addressing.
From the standpoint of instruction sets in a processor, computer architects have developed two general approaches: complex instruction set computer (CISC) processors provide an extensive set of optimized instructions to address all sorts of special-purpose needs, while reduced instruction set computer (RISC) processors provide, in general, a smaller set of more simplified and uniform instructions from which more complex instructions can be constructed. The wide range and complexity of the instructions provided by CISC processors contribute to the complexity of the hardware and reduce the efficiency of a chip as a whole. Techniques such as microcoding and trap and emulate have made the increasing complexity of the CISC processor hardware design more manageable. However, for high end CISC processors, where optimization of speed and performance is the goal, implementation of the hardware remains highly complex and very expensive.
The contrasting RISC approach aims to simplify all of the architectural aspects of the design of a machine so that its implementation can be made more efficient. RISC designs take advantage of the fact that some of the more elaborate CISC instructions are either not used at all by most compilers, or if they are, they are used very rarely. There is, therefore, an emphasis on a smaller number of uniform instruction formats, preferably all of the same size. The regularity of these formats simplifies the instruction-decoding mechanism and allows for the use of pipelining in which several instructions are being executed at once.
Simple and uniform instruction formats, pipelining of several instructions, simplified memory addressing and register-to-register operations are some of the typical features of a RISC processor design. The combination of these techniques has made possible high performance RISC processors with very efficient architectures and maximum throughput (i.e. execution rates of one instruction per clock cycle). Further refinements made to these techniques has produced a family of successful RISC processors based on the MIPS architecture (R2000, R3000, R4000 and R6000) developed by MIPS Technology, Inc., a wholly-owned subsidiary of Silicon Graphics, Inc. of Mountain View, Calif.
RISC processor designs continue to push the state of the art to further increase efficiency and throughput to achieve execution rates of even greater than one instruction per clock cycle. However, while this trend has resulted in very high performance RISC processor chips, the power dissipation and cost have increased in parallel. As a result, portable computing devices such as desktop and notebook computers have not benefited from the high performance levels provided by RISC processors.
From the above it can be appreciated that there is a need for a low-power, low-cost RISC processor that provides the high performance advantages of RISC designs with reduced cost and power dissipation for portable computing devices.